ASIC Verification Methodologies

this is a blog for learning verification methodologies.

Tuesday, 13 August 2013

This is Nagesh, Working as Verification Engineer.

Posted by Nagesh at 09:43

Nagesh: Bengaluru/Bangalore, Karnataka, India; • Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog. • Expertise with TLM, OVM, UVM verification environment. • Good understanding of the ASIC and FPGA design flow and Digital Design. • Expertise in RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis. Verification Methodologies: Coverage Driven Verification, Assertion Based Verification, Transaction Based Verification, Constrained Random Verification

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