ASIC Verification Methodologies
this is a blog for learning verification methodologies.
Thursday 25 September 2014
›
Hello, Can any body tell me how to exclude one coverbin for particular instance. Means if I want to create two instance of same cover gro...
Tuesday 27 August 2013
›
The Universal Verification Methodology (UVM) is a standard verification methodology from the Accellera Systems Initiative that was develope...
Sunday 25 August 2013
›
Difference b/w send_item(), and `uvm_do_* ? Ans: `uvm_do_* will create before randomization and call send_request(), but send_item(...
Tuesday 13 August 2013
Hii friends......
›
This is Nagesh, Working as Verification Engineer.
Saturday 24 November 2012
Specification
›
SPI MASTER CORE SPECIFICATION INTRODUCTION: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data l...
1 comment:
Home
View web version