ASIC Verification Methodologies

Hello, Can any body tell me how to exclude one coverbin for particular instance. Means if I want to create two instance of same cover gro...

The Universal Verification Methodology (UVM) is a standard verification methodology from the Accellera Systems Initiative that was develope...

Difference b/w  send_item(), and `uvm_do_* ? Ans:      `uvm_do_* will create before randomization and call send_request(), but send_item(...

This is Nagesh, Working as Verification Engineer.

SPI MASTER CORE SPECIFICATION INTRODUCTION: The   Serial Peripheral Interface Bus   or   SPI bus is a   synchronous   serial data l...